1. Field of the Invention
The present invention relates to the technical field of liquid crystal displaying, and in particular to a thin film transistor (TFT) with a parasitic capacitance compensation structure and a liquid crystal display device using the TFT.
2. The Related Arts
Liquid crystal displays are the most commonly used displays, which, when compared to the traditional cathode ray tube (CRT) displays, show various advantages including compact device size, low power consumption, and low voltage driving. The liquid crystal display device has a display zone that is composed of a plurality of pixel areas. Each pixel area is an area delimited by two scan lines and two data lines and comprising a thin film transistor (TFT) that serves as a switch and a pixel electrode.
As shown in FIG. 1, which is a schematic view showing a conventional thin film transistor, the thin film transistor comprises a gate terminal 100, an insulation layer (not shown) formed on the gate terminal 100, a semiconductor silicon layer 200 formed on the insulation layer, a source terminal 300 formed on the semiconductor silicon layer 200, and a drain terminal 400. The semiconductor silicon layer 200 is formed between the gate terminal 100 and the source terminal 300 and between the gate terminal 100 and a portion of the drain terminal 400. The drain terminal 400 is electrically connected to a pixel electrode (not shown). The source terminal 300 is electrically connected to the data line 500. The drain terminal is of an inverted L-shape. The drain terminal 400 and the gate terminal 100 overlap each other via the insulation layer so as to form a first overlap region A and also overlap each other via the semiconductor silicon layer and the insulation layer to form a second overlap region B. The first overlap region A and the second overlap region B respectively induce a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance and the second parasitic capacitance together form a parasitic capacitance Cgd between the drain terminal 400 and the gate terminal 100. When shifting occurs in the manufacture of a thin film transistor, the areas of the first overlap region A and the second overlap region B are changed and this leads to variation of the parasitic capacitance Cgd.
According to the formula of feed-through voltage, the feed-through voltage ΔV is as follows:
      Δ    ⁢                  ⁢    V    =                    C        gd                              C                      1            ⁢            c                          +                  C          s                +                  C          gd                      ×          V      p_p      where C1c is capacitance generated by the liquid crystal cell, Cs is storage capacitance, Cgd is capacitance of the coupling capacitor between the gate terminal 100 and the drain terminal 400, namely the parasitic capacitance, and Vp—p is voltage variation of the gate terminal 100.
It can be seen that the parasitic capacitance Cgd influences the magnitude of the feed-through voltage. The larger the parasitic capacitance Cgd is, the larger the feed-through voltage will be and the lower the central potential level between positive and negative half cycles will be; the smaller the parasitic capacitance Cgd is, the smaller the feed-through voltage will be and the higher the central potential level between the positive and negative half cycles will be. The inconsistency of the feed-through voltage leads to irregular central potential level between the positive and negative half cycles, making the liquid crystal display panel showing inconsistent brightness or causing flicking problems.
To overcome such a problem, as shown in FIG. 2, an end of the drain terminal 400′ is extended to show a T-shape and a through slot 120′ is formed in the gate terminal 100′ at a corresponding site in order to reduce the variation of Cgd when changes occur in the manufacture process. However, the parasitic capacitance generated by an overlap region between the extension section 420′ of the drain terminal 400′ and the gate terminal 100′ and the parasitic capacitance generated by an overlap region between the drain terminal 400′ and the gate terminal 100′ via the semiconductor silicon layer 200′ cannot compensate each other. Apparently, further improvement is desired.